Subject Code |
Subject Name |
URL |
21EC71 |
Advanced VLSI |
https://youtube.com/playlist?list=PLcwp2fRcIXJU8hnEEUwHLaSJvnLsGQqaA&feature=shared |
18EC642 |
Artificial Neural Networks |
https://youtube.com/playlist?list=PLcwp2fRcIXJX2duUe6-JEwKcXWiTSb0x1&feature=shared |
18EC646 |
Python Application Programming |
https://youtube.com/playlist?list=PLcwp2fRcIXJU2zi8-RVs9I8q2meGymb-C&feature=shared |
18EC63 |
Microwave and Antennas |
https://youtube.com/playlist?list=PLcwp2fRcIXJXeV2Z6iX5hpZImffBGqNxL&feature=shared |
18EC42 |
Analog Circuits |
https://youtube.com/playlist?list=PLcwp2fRcIXJVvr4Bl-CY1CgpsuYHvGSDZ&feature=shared |
18EC46 |
Microcontroller |
https://youtube.com/playlist?list=PLcwp2fRcIXJVob3xCgcvXHw-ejSsAJlEJ&feature=shared |
18EC34 |
Digital System Design |
https://youtube.com/playlist?list=PLcwp2fRcIXJUfkiaPTmkkVirPfRzfF8Zy&feature=shared |
Study Materials
Faculty Name
|
Semester
|
Subject Name
|
Module
|
Video Title with link
|
Prof. V. K. Patil
|
IV
|
Analog Circuits
|
Module 4
|
Introduction to Operational Amplifiers : https://youtu.be/Z7uSxteN9Gc
|
Abstract symbol of op amp : https://youtu.be/Q5IVGI-8vQU
|
||||
Characteristics of ideal op amp: https://youtu.be/b1-a71R5PRQ
|
||||
Differential amplifier : https://youtu.be/vLuPcAUFmUc
|
||||
Closed loop configuration: https://youtu.be/DFLcfvjH_6g
|
||||
Output voltage expressions: https://youtu.be/QIJKrlERkJg
|
||||
Summing amplifier : https://youtu.be/GRu75O-V32w
|
||||
Differentiator : https://youtu.be/_YJlttRyVB0
|
||||
Integrator : https://youtu.be/CDAWPZU2Cdw
|
||||
Op amp parameters: https://youtu.be/6lba7xSzthc
|
||||
Prof. V. K. Patil
|
IV
|
Analog Circuits
|
Module 5
|
Op amp with feedback : https://www.youtube.com/watch?v=0mX_CCVtqro
|
Gain and Bandwidth : https://www.youtube.com/watch?v=wfkzz1rg-xk
|
||||
Comparator : https://www.youtube.com/watch?v=k9zQjEaKtfk
|
||||
Schmitt Trigger : https://www.youtube.com/watch?v=5-ohKRWeod4
|
||||
Examples on Schmitt Trigger : https://www.youtube.com/watch?v=ZzMznw9VD-0
|
||||
Instrumentation Amplifier : https://www.youtube.com/watch?v=pSctPegtZfc
|
||||
V to I Converter : https://www.youtube.com/watch?v=DeDk0Rl3Oa0
|
||||
I to V converter : https://www.youtube.com/watch?v=OMnZehJNGCY
|
||||
Precision Rectifier : https://www.youtube.com/watch?v=5HweBajP-5g
|
||||
Zero Crossing Detector : https://www.youtube.com/watch?v=GjsDfqfcrBo
|
||||
Active LPF & HPF : https://www.youtube.com/watch?v=gEeF8sEQTEc
|
||||
Active BPF & BSF : https://www.youtube.com/watch?v=dmPIydL0lyM
|
||||
Introduction to ADC & DAC : https://www.youtube.com/watch?v=HicZcgdGxZY
|
||||
Binary Weighted ADC : https://www.youtube.com/watch?v=PoOm_G4s1dE
|
||||
Single slope & dual slope ADC: https://www.youtube.com/watch?v=2gF_nfaBV_0
|
||||
Successive Approximation ADC : https://www.youtube.com/watch?v=h0CGtr4SC9s
|
||||
Introduction to 555 Timer : https://www.youtube.com/watch?v=EGmreVQ-yNM
|
||||
Monostable Multivibrator using 555 Timer : https://www.youtube.com/watch?v=ypV6gdIJJU4
|
||||
Astable Multivibrator using 555 Timer :
|
||||
Prof. P. L. Gurav
|
IV
|
Microcontroller (18EC46)
|
Module 3
Module 4
|
Time Delay Calculation https://www.youtube.com/watch?v=NhNxVbaVfvY&t=2s
|
Time Delay Calculation – Program 1
|
||||
Time Delay Calculation – Program 2
|
||||
Time Delay Calculation – Program Nested Loop
|
||||
200 ms AT89C51– Program https://www.youtube.com/watch?v=l4GlznAEgT0&t=3s
|
||||
200 msDS89C4X0 – Program https://www.youtube.com/watch?v=sHF-YELN7sg&t=4s
|
||||
1 second Time Delay Program https://www.youtube.com/watch?v=t9KdXR30Du0&t=2s
|
||||
Factorial Program https://www.youtube.com/watch?v=QudvSj40CN0&t=116s
|
||||
Counting 1’s & 0’s in 8 – bit Data Program https://www.youtube.com/watch?v=rMsV96-Aaww&t=3s
|
||||
Sorting numbers in Ascending Order
|
||||
I/O Ports & Bit Addressability
|
||||
Single Bit Instructions
|
||||
I/O Ports & Bit Addressability - Programs
|
||||
External Block Move without Overlap
|
||||
|
|
Module 4
|
Timer & Serial Port
|
|
Timer Mode 1 Programming
|
||||
Finding values to be loaded in timer registers
|
||||
Stack Program 2
|
||||
Prof. P. L. Gurav
|
VI
|
ARM Microcontroller & Embedded Systems (17EC62)
|
Module 3
|
A Typical Embedded System
|
Application Specific Integrated Circuits (ASICs)
|
||||
Types of ROM & RAM Memory
|
||||
Sensors, Actuators & I/O Subsystems
|
||||
Onboard Communication Interface
|
||||
Prof. Raju Hebbale
|
VI
|
VLSI Design
|
Module 3
|
Implementation of ALU using Adder
|
Further Consideration of Adder
|
||||
Manchester Carry Chain
|
||||
Carry Select Adder
|
||||
Carry Skip Adder
|
||||
VI
|
VLSI Design
|
Module 4
|
Subsystem Design
|
|
Switch Logic
|
||||
Gate Logic
|
||||
Clocked CMOS & Pseudo NMOS Logic
|
||||
Dynamic & Domino CMOS Logic
|
||||
Parity Generator & Multiplexer
|
||||
Prof. Vanita Abbigeri
|
VI
|
Digital Switching Systems
|
Module 3,4, 5
|
Digital Switching Systems Module 3 Part 2 session https://youtube/SBvlOVUVz5Q
|
Digital Switching Systems Module 3 Part 2 session 3
|
||||
Digital Switching Systems Module 3 Part 2 session https://youtube/K1K4uFtpU-E
|
||||
Digital Switching Systems Module 3 Part 2 session https://youtube/hUCIbKU0N_w
|
||||
Digital Switching Systems Module 4 Part 2 Session1
|
||||
Digital Switching Systems Module 4 Part 2 Session 2
|
||||
Digital Switching Systems Module 4 Part 2 Session 3
|
||||
Digital Switching Systems Module 5 Part 1 Session 1
|
||||
Digital Switching Systems Module 5 Part 1 Session 2
|
||||
Digital Switching Systems Module 5 Part 1 Session 3
|
||||
Digital Switching Systems Module 5 Part 1 Session 4
Digital Switching Systems Module 5 Part 2 Session 1
|
||||
Prof. Vanita Abbigeri
|
VIII
|
Fiber Optics & Networks
|
Module 4
|
Active optical components of FO&N Module 4
|
Tunable optical filters of FO&N Module 4
|
||||
Active optical components Part 2 of FO&N Module 4
|
||||
MZI topic in Fiber optics & Networks Module 4
|
||||
Prof. Sunayana Bisalapur
|
Vl
|
DSDV
|
Module 2
|
FIFO example: https://youtu.be/9Va0jtKArig
|
ECCpart1:https://youtu.be/bg2ukXg0Nh
|
||||
ECCpart2:https://youtu.be/HYpkDW94AI8
|
||||
Module 3
|
Counter part1:https://youtu.be/DrK1wI9ZR8w
|
|||
Counterpart2:https://youtu.be/yBDMdBA-OHs
|
||||
Signal Integrity:https://youtu.be/Fkz0uRxUAQE
|
||||
Differential signaling:https://youtu.be/yBWdqCJFI1o
|
||||
Module 4
|
O devices:https://youtu.be/n1G7BYGVeuc
|
|||
I/O devices1:https://youtu.be/zDG1gYufKh0
|
||||
Example:https://youtu.be/dQgWU2V2VPk
|
||||
Output Devices:https://youtu.be/Ns9SQzaLMHc
|
||||
Autonomous I/O controller:https://youtu.be/A_uZAcJX9uc
|
||||
I/O controller:https://youtu.be/23kbyLnoTRQ
|
||||
Multiplexed buses:https://youtu.be/qTVJuNSsOBA
|
||||
Prof. Jyoti C. K.
|
VI |
DC |
Module 3 |
QPSK signal explained : https://www.youtube.com/watch?v=K7coPnze2h0 |
QPSK signal constellation: https://www.youtube.com/watch?v=t-FYiwAuCz4 |
||||
QPSK generation & Detection : https://www.youtube.com/watch?v=xLFdHledvPg&t=19s |
||||
DC_Module3_Probability of Error in QPSK : https://www.youtube.com/watch?v=Pmx2TgeggJM |
||||
DC_ module 3_M-ary PSK(2) : https://www.youtube.com/watch?v=dJHdwXZEsR8 |
||||
Binary Frequency Shift Keying : https://www.youtube.com/watch?v=3qUg_ajD2ao&t=40s |
||||
Binary Frequency Shift Keying - Continued : https://youtu.be/8R2pVnjdZyg |
||||
Error probability of BFSK : https://www.youtube.com/watch?v=acdFHSTGMIg&t=46s |
||||
PAM Introduction : https://www.youtube.com/watch?v=_Mjqk5hqUlM&t=370s |
||||
M-ary QAM : https://www.youtube.com/watch?v=v8WAt86z9uU |
||||
M- ary QAM example : https://youtu.be/QpgBhA74CJA |
||||
Non coherent Detection of BFSK : https://youtu.be/QSU_MP98WxQ |
||||
DPSK : https://youtu.be/Gf77xYop698 |
||||
DPSK 1 : https://youtu.be/mIqiJu_bXvc |
||||
DPSK 1 Continued : https://youtu.be/-vdbTy6vqPU |
Staff Name
|
Semester
|
Subject Name
|
Module
|
Video Title with link
|
Prof. B. N. Choukimath
|
IV
|
Control systems
|
4
|
Stability analysis using RH criteria
|
Prof. Raju Hebbale
|
VI
|
VLSI Design
|
3
|
Scaling of MOS Circuits
|
Scaling of MOS Circuits
|
||||
Subsystem Design Process
|
||||
Subsystem Design Process
|
||||
Subsystem Design Process
|
||||
Illustration of design Process https://youtu.be/N5tBqUJIesc
|
||||
Standard Adder Element https://youtu.be/BpUMa3vtytU
|
||||
Prof . Jyoti C. K.
|
VI
|
Digital Communication
|
2
|
Optimum Receivers using Coherent Detection
|
Optimum Receivers using Coherent Detection continued |
||||
Optimum Receivers using Coherent Detection-Correlation Receiver |
||||
Optimum Receivers using Coherent Detection-Matched Filter |
||||
3
|
Binary Phase Shift Keying (BPSK)
|
|||
BPSK continued
|
||||
Quadrature hase Shift Keying (QPSK) |
||||
VIII
|
Radar Engg
|
3
|
MTI and pulse Doppler radar |
|
MTI and pulse Doppler radar continued |
||||
MTI and pulse Doppler radar continued |
||||
Prof. Praveen Gurav
|
Vl
|
DSDV
|
2
|
FIFO example: https://youtu.be/9Va0jtKArig
ECCpart1:https://youtu.be/bg2ukXg0Nh
ECCpart2:
|
VI
|
DSDV
|
3
|
Counter part1:
Counterpart2:
PLD1:
PLD2:
GAL1:
GAL2:
Signal Integrity:
Differential signaling:
|
|
Prof. Vaneeta Abbigeri
|
VI
|
Digital Switching Systems
|
3
|
17EC654- Digital switching systems Module 3 Part 1
|
Unit of traffic topic in Digital switching systems module 3 Part 1
|
||||
Congestion topic in Digital switching systems module 3 Part 1
|
||||
Mathematical model topic in Digital switching systems module 3 Part 1
|
||||
State transition for N trunks topic in Digital switching systems module 3 Part 1
|
||||
Lost call systems of Digital switching systems Module 3 Part1
https://youtu.be/xb72csj49LA |
||||
Traffic performance topic in Digital switching systems module 3 Part 1
https://youtu.be/xsqNBC9fKZE |
||||
Sequential selection of Digital switching systems Module 3 Part1
https://youtu.be/CXZ0u6eA7Ec |
||||
Queuing systems in Digital switching systems module 3 Part 1
https://youtu.be/xTgcEvrbIYU |
||||
Delay table in Digital switching systems module 3 Part 1
https://youtu.be/QO91OnglQxA |
||||
17EC654- Digital switching systems Module 3 Part 2
https://youtu.be/5UuMcCIQkhY |
||||
VIII
|
Fiber Optics & Networks
|
4
|
WDM of Fiber Optics & Networks Module 4
https://youtu.be/IRP2hrW_bNI |
|
Optical isolators of Fiber Optics & Networks Module 4
https://youtu.be/Uzc85ZW-hb8 |
||||
Optical circulators of Fiber Optics & Networks Module 4
https://youtu.be/hRyDnhjJDBM |
||||
DTFF topic of Fiber Optics & Networks Module 4
https://youtu.be/BEDKIQR6F-g |
||||
Prof. V. K. Patil
|
IV
|
Analog Circouits
|
4
|
Introduction to Operational Amplifiers : https://youtu.be/Z7uSxteN9Gc
|
Abstract symbol of op amp : https://youtu.be/Q5IVGI-8vQU
|
||||
Characteristics of ideal op amp: https://youtu.be/b1-a71R5PRQ
|
||||
Differential amplifier : https://youtu.be/vLuPcAUFmUc
|
||||
Clossed loop configuration: https://youtu.be/DFLcfvjH_6g
|
||||
Output voltage expressions: https://youtu.be/QIJKrlERkJg
|
||||
Summing amplifier : https://youtu.be/GRu75O-V32w
|
||||
Differentator : https://youtu.be/_YJlttRyVB0
|
||||
Integrator : https://youtu.be/CDAWPZU2Cdw
|
||||
Op amp parameters: https://youtu.be/6lba7xSzthc
|
||||
Prof. Vijay L. H.
|
IV
|
Signals & Systems
|
2
|
Derivation to Convolution Sum,https://youtu.be/Nlu-_LX6YGQ
Convolution sum – example 1,https://youtu.be/IGBmcIY8oCc
Convolution sum – example 2.https://youtu.be/wbzTI12A7s0
Convolution sum – example 3.https://youtu.be/jryL2Ax1GP8
Convolution sum – example 4,https://youtu.be/BNspttjvJJE
Convolution sum – example 5,https://youtu.be/FhxSxHMLoaM
Convolution sum – example 6.https://youtu.be/FhxSxHMLoaM
|
3
|
Z Transform for finite duration sequences,
Z Transform of Positive time exponential sequence
Z Transform of Negative time exponential sequence
Z-Transform for Negative exponential continued and Double sided exponential sequences
Example of Z transform
Properties of ROC and Properties of Z transform-Linearity
Properties of Z Transform – Time Shifting and Scaling in Z domain
Properties of Z transform – Time reversal
Properties of Z transform – Differentiation in Z domain and Convolution in time domain
|